1. Field of the Invention
The present invention relates to a CMP (chemical mechanical polishing) method for planarizing the surface of a wafer, used in the course of a process for production of a semiconductor device having damascene interconnection and through holes, as well as to a polishing solution used in the CMP method.
2. Description of the Related Art
In semiconductor integrated circuit devices having multi-layer wiring, a lower wiring is formed on a substrate; thereon is formed an insulating film; in the insulating film are formed via holes for connecting the lower wiring with an upper wiring to be formed later; then, a metal film is formed on the insulating film; the metal film is subjected to patterning by lithography and etching to form an upper wiring. In this case, since the surface of the insulating film has unevennesses owing to the presence of the lower wiring, various inconveniences arise when an upper wiring is formed with the above unevennesses are left as they are. That is, formation of fine pattern is difficult because the lithography necessary for formation of upper wiring need be conducted for the metal film having surface unevennesses; further, leakage may appear in the insulating film or the upper wiring may cause disconnection. Therefore, the surface of the insulating film (which becomes a base for upper wiring formation) is preferred to be planarized as sufficiently as possible.
As a technique for such planarization, chemical mechanical polishing (CMP) is in wide use. Description is made below on a conventional method for formation of damascene interconnection by CMP, with reference to FIG. 4.
Firstly, as shown in FIG. 4(a), a silicon nitride film 2 (thickness=100 nm) and a silicon oxide film 3 (thickness=1,000 nm) are formed in this order on a silicon substrate 1; then, in the silicon oxide film 3 are formed, by dry etching, a plurality of dents reaching the silicon nitride film 2.
Next, as shown in FIG. 4(b), on the whole surface of the resulting wafer is formed, by sputtering, a barrier metal 4 made of Ta and TaN. The film thickness is controlled at 20 nm. Successively, thereon is formed, by sputtering, a seed metal film (not shown) made of copper, for growing copper plating thereon. Successively, the resulting wafer is immersed in an aqueous copper sulfate solution of about 25.degree. C. and electrolytic plating is conducted to form a copper plating film 5. The thickness of the copper plating film 5 is controlled at about 900 nm at the flat portion. This state is shown in FIG. 4(b).
The wafer after plating is subjected to annealing at 300.degree. C. for about 30 minutes. Thereby, the grain size of copper is made larger and its resistance becomes smaller.
Next, the copper plating film 5 is polished by CMP for planarization of wafer. CMP is conducted ordinarily by using a polishing apparatus such as shown in FIG. 5. In FIG. 5, a wafer 10 refers to a wafer obtained by forming films on a substrate 1 in the manner mentioned above. The wafer 10 is placed beneath a wafer carrier 11. While the film-side surface of the wafer 10 is contacted with a polishing pad 12, both the wafer carrier 11 and the polishing pad 12 are rotated at respective given speeds. Between the wafer 10 and the polishing pad 12 is fed a polishing solution 14 from a discharging port 13 by a pump 15.
As the polishing solution 14, there is generally used a slurry in which an abrasive such as alumina particles, silica particles or the like is dispersed. Ordinarily, a slurry for metal polishing or a slurry for insulating film polishing is used depending upon the progress of polishing, because the polishing speed of metal film and the polishing speed of insulating film are greatly different and no sufficient planarization is obtained unless a different polishing solution is used depending upon the kind of the polishing surface. For example, a slurry for metal polishing is used in the stage of FIG. 4(b), and a slurry for insulating film polishing is used in the stages of FIGS. 4(c) to 4(d).
Various proposals have been made on the selection of the polishing solution 14. In JP-A-8-124886 is disclosed a method of using first a polishing solution for metal, then a neutral polishing solution and lastly an alkaline polishing solution for insulating film. In JP-A8-139060 is disclosed a method of polishing a metal film using an acidic polishing solution and then polishing an insulating film using an alkaline polishing solution. Thus, by appropriately selecting the kind of polishing solution depending upon the kind of wafer surface, planarization by a simple process is made possible.
Then, polishing is continued for a given length of time; a state shown in FIG. 4(d) is attained; and damascene interconnection is completed.
The above-mentioned conventional technique, however, has had the following problems.
The first problem is generation of dishing in buried metal parts. In the CMP of FIG. 4(c), a sufficient polishing time must be taken so that no barrier metal film 4 remains on the silicon oxide film 3. The polishing speed of the copper plating film 5 is very large as compared with that of the barrier metal film 4 and is ordinarily at least 30-fold as compared with that of Ta type metal generally used as a barrier metal film. Therefore, as shown in FIG. 3(c), the polishing of copper plating film 5 proceeds excessively as compared with that of the barrier metal film 4, in the step conducted after the exposure of the barrier metal film 4 and the center of the metal film 3 is dented as shown in FIG. 7. This phenomenon is called dishing. Since the barrier metal film 4 on the insulating film 3 must be removed substantially completely, slightly excessive etching is necessary; hence, certain dishing inevitably generates ordinarily. This generation of dishing of copper layer results in local increase of resistance. Further, electromigration may be induced, resulting in reduced reliability of device.
A second problem is generation of erosion. As described above, a slightly excessive polishing time is necessary in the CMP of FIG. 4(c). The polishing speed of copper plating film 5 is very large as compared with those of the barrier metal film 4 and the silicon oxide film 3 and the copper plating film is polished faster. Therefore, In the CMP conducted after the barrier metal film 4 has been exposed, the speed of CMP differs between the concentrated-wiring region and the isolated-wiring region. That is, the pressures applied to the barrier metal film 4 and the silicon oxide film 3 are higher in the concentrated-wiring region where a number of buried parts of copper plating film 5 are present, than in the isolated-wiring region where a very small number of buried part of copper plating film 5 is present. As a result, CMP proceeds excessively in the concentrated-wiring region and surface denting takes place as shown in FIG. 4(d). This phenomenon is called erosion.
The generation of erosion results in reduction in flatness of wafer surface. The reduction in flatness is more striking in a multi-layer structure and induces problems such as short-circuiting in wiring, and the like. Further, when damascene interconnection has been formed, the sectional area becomes smaller and the resistance becomes larger.
As described above, the erosion and dishing generate owing to the difference in polishing speed between copper and barrier metal film or insulating film. In the practical process for production of semiconductor device, however, the erosion and dishing are further promoted by the process parameters other than mentioned above. Description is made on this below.
FIG. 6(a). is a drawing showing a state of the surface of a wafer when a polishing solution has been fed onto the surface. The wafer and a polishing pad are being rotated at about the same speeds in the same direction. When polishing is conducted under such conditions, the outer circumference of wafer has a larger speed than the inner circumference of wafer and consequently contacts with a larger area of pad per unit time. (See FIG. 6(b)). As a result, polishing proceeds more in the outer circumference of wafer than in the inner circumference of wafer. Further, with respect to the distribution of polishing solution on wafer, there arises non-uniformity between the outer circumference and the inner circumference. The polishing solution dropped on the polishing pad migrates from the outer circumference of wafer toward the inner circumference of wafer and spreads over the entire surface of wafer. In this case, the time-average concentration of polishing solution is higher in the outer circumference of wafer than in the inner circumference of wafer. This also becomes a parameter which makes the polishing of outer circumference more than that of inner circumference. The wafer having, on the surface, a metal film and an insulating film has upward warpage at the film side. Therefore, when the wafer is pressed against the polishing pad 12 to conduct polishing, the warpage remains to a certain degree and the outer circumference of wafer tends to be polished more.
Thus the outer circumference of wafer tends to be polished more than the inner circumference of wafer, owing to various parameters of process. Therefore, in order to achieve flatness over the entire surface of wafer, the polishing time need be taken even longer. This makes erosion and dishing more striking.